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*Most of these are works in progress

Memory Notes: Types of Memory: - DRAM: Dynamic random access memory (50 - 70ns access time) - typical main memory type - 1 capacitor stores a value, 1 transistor reads/writes this cap - Capacitors needed to be refreshed to maintain state, hence "dynamic": a refresh consists of reading and writing back value to cap via transistor - Cap charge (state) can be maintained for a couple miliseconds w/o requiring refresh - SDRAM: DRAM + a clock, resulting in "Synchronous" DRAM, eleminates need for proc & mem to sync, instead transferring successive bytes to proc in a burst - DDR SDRAM: "Double Data Rate" SDRAM. Data transfers on both the rising & falling edges of the clock, doubling bandwidth for given bandwidth & clock speed - DDRi SDRAM: i refers to DDR technology version - DDRi-xxxx: xxxx is #transfers (millions) per second. Ex: DDR4-3200 can do 3200 million transfers per second, which means it operates at 1600Mhz (clock speed) - DIMM: "Dual Inline Memory Module" typically containing 4-16 DRAMs, organized to be (usually) 8 bytes wide, resulting in ie 8x32000=256000 MBps transfer speed - SRAM: Static random access memory (.5 - 2.5ns access times) - typical cache memory type - No need to refresh, so access times very close to cycle times - Typically 6-8 transistors used per bit of storage to prevent read disturbances - Minimal power requirements - Modern CPUs almost always physically include their cache SRAM - Indefinite data retention given constant power - Flash Memory: nonvolatile memory (5K - 50Kns access times) - secondary memory, or "storage" - EEPROM: "electrically erasable programmable read-only memory" - writes can wear out (degrade) EEPROM - Wear Leveling: processes of remapping frequently rewritten blocks to spread-out wear. Reduces performance. - Magnetic Disk: long-term, nonvolatile (5M - 20Mns access times) - long-term storage, very cheap Cache Notes: Locality: - Temporal: The tendancy for recently referenced location to be referenced again soon. - Spatial: The tendancy for references to be followed by nearby (proximate) location references. Block (or line): The minimum unit of information that can be present or not present in a cache. Hit rate: the fraction of memory accesses found in a level of the memory hierarchy Miss rate: the fraction of memory accesses NOT found in a level of the memory hierarchy Hit time: The time required to access a level of memory hierarchy, including the time needed to determine whether the access is a hit or miss Miss penalty: The time required to fetch a block into a level of the memory hierarchy from the lower level, including the time to access the block, transmit it from one level to the other, insert it in the level that experienced the miss, and then pass the block to the requestor. Types of Cache: - Direct-Mapped: A cache structure in which each memory location is mapped to exactly one location in cache - Typical Mapping Scheme: (Block Address) mod (# blocks in cache) - Fully-Associative: A cache structure in which a block can be placed at any location in the cache - Due to design, each block must be searched, which can be slow - To improve performance, the search is done parallel to a "comparator" associated with each cache entry. - Comparators increase hardware cost, making this type of cache structure only practical for small cache sizes w/ small #s of blocks. - Set-Associative: A cache structure that has a fixed number of locations (>2) where each block can be placed. - An n-way set associative cache consists of a number of sets, each of which consists of n blocks. - Each block in memory maps to a unique set in the cache, given by the index field. - A block can be placed in any slot inside its proper set. - Set Associative caches know set location like direct-mapped, but must then search for a block in a given set like fully-associative. - Set containing a memory block is given by: (Block Number) mod (# sets in cache) - 1-Way set-associative effectively -eq direct-mapped, and m-Way set-associative effectively -eq fully-associative w/ m entries Cache Terms: - Tag: a field in a table used for a memory hierarchy that contains the address information required to determine whether a word in the cache corresponds to a request. - The tag need only contain the upper bits of a the address, that is the bits which are NOT an index into the cache. - Valid Bit: a field in the table used for memory hierarchy that indicated that the associated block in the heirarchy contains valid data - Cache Index: part of referenced address used to select the block (line) within the cache - A block's index + its tag uniquely identify the physical memory address of the word contained in the block. - Out of order: An out of order processor is capable of executing other instructions while waiting for a cache miss - An in-order processor must wait (stall) when a cache miss results in lower heirarchical memory access. - Specific Steps in In-Order Instruction Cache miss: - Send Program Counter relative to beginning of instruction (probably PC - 4) to memory - Memory performs read - Write result of memory read to cache: data->cache line's data section, upper address bits->cache line's tag field, 1->cache line's valid bit - Restart instruction from beginning (probably PC - 4), which will now result in a cache hit. - Write Through: A scheme in which writes always update both the cache and the next lower level of memory hierarchy, ensuring data consistency - Write Back: A scheme that handles writes by updating values only to the block in the cache, then writing the modified block to lower levels when it is to be replaced. - Write Buffer: A queue that holds data while the data is waiting to be written to memory, allowing the processor to continue executing other instructions. - LRU: "Least Recently Used" is a cache replacement policy whereby the block replaced is the one which has been unused for the longest time. - LRU is the most common replacement scheme.